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From Basic to In-depth Understanding DDR Write Leveling
1. Why is Write Leveling needed?
It all starts with PCB routing. Boss Zhao Renfan assigned Xiao Tang a task: to route a DDR3 design. The DQS and DQ signals are relatively easy to route because each DRAM chip has dedicated signals. Soon, Xiao Tang finished routing them (assuming each chip has a 1-bit width):
However, the Clock, Address, and Command signals are a bit more troublesome because they are shared by all the chips. So how should they be routed?
2. First option: Double-T topology
The first way is the Double-T topology – one splits into two, and two split into four. The advantage is that the distances from the controller to each DDR chip can be made equal by constraints, so no separate adjustment is needed when operating each chip. However, this topology is not very friendly to signal integrity: the stubs are longer, reflections can be more severe, making it unsuitable for DDR3 or higher-frequency applications.
3. Second option: Fly-by topology
The second way is Fly-by, i.e., a daisy-chain topology – one chip after another, with termination placed after the last chip.
The advantage is improved signal integrity, but the problem is that the distances from the controller to each chip are now different -some are closer, some farther. So how should Clock and Data be sent? If we align to the closest chip, the farther chips will be unhappy (they won’t sample correctly); if we align to the farthest chip, the nearer ones won’t be happy; if we choose a middle point, both sides are dissatisfied.
Just like the common issues faced by any large organization, group, or society, not every policy or decision can satisfy everyone. However, unlike those organizations, which can sacrifice the interests of a minority to please the majority, the DDR controller cannot do that – it must satisfy all chips, otherwise the entire systme will not work properly.
What to do then?
This is where Write Leveling comes in.
4. What is Write Leveling?
The purpose of Write Leveling is to ensure that when the DQS signal reaches each DRAM chip, its rising edge is aligned with the rising edge of the clock (CK).
How is it done?
- The controller sets the A7 bit of the MR1 register to HIGH, putting the DRAM chip into Write Leveling mode;
- The controller sends CK and DQS with their rising edges aligned;
- Although CK and DQS are aligned at the controller side, because their trace lengths to the DRAM chip are different, by the time they arrive at the DRAM, they are most likely misaligned. Moreover, the phase difference varies for each chip. The DRAM chip then uses the rising edge of the DQS it receives to sample the CK level, and outputs the sampled result on its DQ pin;
- The controller keeps delaying the DQS signal for each chip individually until it sees a 0-to-1 transition on the coresponding DQ signal for that DQS – this indicates that the rising edge of DQS is aligned with the rising edge of CK;
- The controller records the delay value for each chip’s DQS. Later, when it sends DQS to that chip, it will apply this delay value to ensure CK and DQS are aligned;
- The controller sets the A7 bit of MR1 to LOW, exiting Write Leveling mode.
A simple animated illustration is provided below for referance.
5. Why must DQS be aligned with CK?
DDR data (DQ) is sampled using the DQS signal, not CK. So why does DQS still need to be aligned with CK? As long as DQS and DQ are aligned, shouldn’t the sampled data be correct?
The main reason is that the operation requires cross-clock domain handling. The data on DQ is not merely sampled and done – it must be stored into the memory cell, and that internal logic circuitry is driven by CK, not by DQS. Therefore, if DQS and CK are not aligned, the internal logic cells may capture incorrect data.
6. Is edge alignment alone sufficient?
You, being clever, have surely already thought of this: Write Leveling only gurantees that the rising edges of DQS and CK are aligned, but it does not determine which rising edge of CK is aligned with DQS.
For example:
Suppose that when sent from the controller, DQS and CK are aligned as follows:
After arriving at the DDR chip, because the DQS trace is usually shorter than the CK trace, DQS often reaches the chip earlier than CK. Their relationship may look like this:
After Write Leveling, DQS is delayed and will align with the T-1 cycle of CK, as shown below:
In this case, although DQS and CK are rising – edge aligned, they are already ooset by one cycle, which will also cause data errors.
What to do then?
This can be resolved throught Write Latency Calibration. The core approach is : the DDR controller writes a fixed pattern of data into the DDR chip, reads it back and checks. If the result is not as expected, it delays DQS one cycle and repeats until the data is correct. The flowchart is as follows:
